Ion implantation systems are used to impart impurities, known as dopant elements, into semiconductor substrates or wafers, also referred to as workpieces. In such systems, an ion source ionizes a desired dopant element, and the ionized impurity is extracted from the ion source as a beam of ions. The ion beam is directed (e.g., swept) across respective wafers to implant ionized dopants within the wafers. The dopant ions alter the composition of the wafers causing them to possess desired electrical characteristics, such as may be useful for fashioning particular semiconductor devices, such as transistors, upon the substrates.
The continuing trend toward smaller electronic devices has presented an incentive to “pack” a greater number of smaller, more powerful and more energy efficient semiconductor devices onto individual wafers. Moreover, semiconductor devices are being fabricated upon larger wafers to increase product yield. For example, wafers having a diameter of 300 mm or more are being utilized so that more devices can be produced on a single wafer. This necessitates careful monitoring and control over semiconductor fabrication processes, including the angle at which the ions are implanted in the wafer.
However, as these device and wafer scaling trends continue, any errors in the implantation angle tend to play a more important role, proportionately, in the electrical characteristics of such devices. For example, such implantation angle errors may be introduced by mechanical misalignment in the implanter and wafer orientation. Other angle errors may be produced because of a divergence of the ion beam or another such angular non-uniformity produced by the implanter between the center and the outer edge of the wafer, sometimes referred to as a “cone angle”.
Further, angle errors or angle variations in halo implants result in misplaced pockets or halos that produce variations in the drive current (Idrive) and threshold voltage (Vt). Because of the misplaced pocket implants, MOS devices often experience a change in the effective gate length Lgeff, a depressed MPY, and other similar channel effects that dramatically alter the electrical parameters of a device. For example, a one degree incident angle variation in the pocket implant of a 90 nm technology device may produce more than a 25% change in one or more electrical parameters of the device. Thus, as devices are highly scaled, angle variations in pocket implants, for example, can play a more important role than dose variations.
Traditionally, such errors in the implantation angle are not detected until the end of the production line in the device parametric data, or by use of expensive additional monitoring equipment. Detection of angular errors at the end of the line after numerous steps have been accomplished tends to cloud the true results. A manual method is also used to measure the implantation angle by performing a physical check, with an angle-measuring ruler according to a vendor recommended procedure. This method, however, may not be accurate enough for many increasingly scaled applications.
One common method of measuring the implantation angle is by the use of modulated reflectance mapping, such as is utilized in Thermawave monitoring equipment. The signal from this technique is expressed in arbitrary “thermawave” (TW) units, which are proportional to implant-induced damage of the silicon crystalline lattice. In this technique, damage tends to increase as the implanter ion beam is tilted off a zero degree (0°) tilt axis or perpendicular to the surface of the wafer. However, as numerous other factors such as variations in the process temperature and ion beam current density also affect damage in the lattice, this technique may lack adequate sensitivity and add unnecessary equipment cost.
Accordingly, as MOS devices are scaled down to support future technologies, it has become increasingly important that the implantation angle be accurately monitored, and that the angle be symmetrically produced, for example, about the zero angle. Thus, there is a need for a method of calibrating the implantation angle of an ion implanter wherein pocket implantations may be improved and effective gate length variations may be mitigated in pocket implantations in the manufacture of semiconductor devices.